This invention relates to a system for marking or erasing the marking of a semiconductor chip package with leads.
Semiconductor chip packages are usually marked for a number of reasons. Thus the packages are frequently marked to identify the manufacturer; they are also marked to identify performance characteristics of the chip such as speed. When the packages are marked to identify a particular company, the package housing may be pre-marked before the housing is used to house the semiconductor chip. However, when the package is to be marked for speed or other performance characteristics, it is frequently desirable to perform the marking after the package is tested. Such testing is normally performed after the leads of the package have been trimmed and formed. The package is simply held manually for marking, as is sometimes performed conventionally. In such circumstances, it may be difficult to avoid bending or otherwise deforming the leads during the marking process. In quad-flat pack (QFP) packages, for example, it is crucial for the leads present on all four sides of the package to remain coplanar. Since the marking process causes a significant force to be applied to the package, it is difficult to avoid bending or otherwise disturbing the coplanarity of the leads during the marking process.
Sometimes semiconductor chip packages may be mismarked so that it is necessary to erase a marking and then remark the package. The erasing and remarking processes are generally performed after the leads are trimmed and formed so that it is difficult to avoid bending or otherwise disturbing the leads during these processes. It is therefore desirable to provide a system for marking or erasing a marking from a semiconductor chip package having leads without bending or otherwise disturbing the leads.